SRAM Performance Enhancement using Transient Negative Bit-Line Voltage Technique

Authors:RAMESH.K, E.VELMURUGAN, C.SADIQ BASHA

0229-0233

An Effective Power Gating Analysis on Sequential Circuits for Low Power Dissipation and Less Occupancy Space

Authors:P.VANNUR, T.SRINIVAS REDDY

0234-0239

Comparison of Agglomerative and Hausdorff Clustering Algorithm in FIR Applications using Multi Bit Flip Flop

Authors:R.ARUN PRASATH, DR. P.GANESH KUMAR, I. DIVONA PRISCILLA

0240-0245

LUT Based Dynamic Power Optimization using Dual VDD/Dual Frequency Controller

Authors:V. SUGANYA, DR. K. SHEELA SOBANA RANI

0246-0249

Study, Implementation and Comparison of Different Multipliers Based on Array, Vedic and KCM using Squarer Mathematics using EDA Tools

Authors:BUKKE SIVARAM NAIK, C. VENKATA SUDHAKAR

0250-0255

An 64 bit Parallel CRC Generation for High Speed Applications

Authors:K.M.V.SUBRAMANYAM, M.NARESH BABU

0256-0260

Design and Implementation of Split Radix Algorithm for Length– 6m DFT using VLSI

Authors:S. SRUTHI, G. NARESH

0261-0267

Implementation of Cordic Based Fast Radix-2 DCT Algorithm

Authors:N. SAI LEELA, R. NAGENDRA

0268-0273